ByteDance builds custom Arm and RISC-V CPUs for AI infrastructure
▼ Summary
– ByteDance is developing custom CPUs for its AI data centers, using both Arm and RISC-V architectures, to reduce reliance on Intel and AMD.
– Intel and AMD have raised server CPU prices by 10-35% per quarter, and ByteDance’s increasing AI budget makes in-house chips a financial necessity.
– RISC-V is favored in China to avoid licensing and export control risks tied to Arm, aligning with Beijing’s push for strategic chip autonomy.
– ByteDance also partnered with Qualcomm to develop AI inference ASICs, expanding its chip diversification beyond CPUs.
– The production challenge remains unclear, as US export controls restrict access to leading-edge foundries like TSMC, while domestic SMIC lags by about two nodes.
ByteDance is developing its own central processing units for the data centres that support its expanding artificial intelligence infrastructure. The parent company of TikTok is pursuing two parallel design tracks, one based on Arm and another on the open-source RISC-V instruction-set architecture, as it determines which approach best fits its long-term needs.
The initiative comes amid a particularly active week for the company’s chip-diversification strategy, driven by both commercial and geopolitical factors. Intel and AMD, which currently supply most of ByteDance’s server CPUs, have raised prices on data-centre-grade processors by 10% to 35% in consecutive recent quarters, according to a Reuters report on Thursday that cited people familiar with the company’s chip programme.
ByteDance’s 2026 AI-infrastructure budget reportedly grew 25% to around 200 billion yuan ($29.4 billion). At that scale, the procurement gap from those price increases becomes material to the company’s overall economics. Building chips in-house has shifted from a theoretical optimisation to a balance-sheet imperative.
The dual-track approach with Arm and RISC-V signals how seriously ByteDance is taking this work. Arm-based server CPUs are the proven path, with Amazon’s Graviton, Microsoft’s Cobalt, and Google’s Axion all in production. RISC-V, the royalty-free instruction set originally developed at Berkeley, is less proven at server scale but is increasingly favoured inside China because it avoids the licensing and export-control exposure tied to Arm’s UK-headquartered, Softbank-owned intellectual property.
Chinese policymakers have explicitly endorsed RISC-V as a strategic-autonomy alternative, and Beijing has been hardening its broader chip-sovereignty posture through 2026.
ByteDance’s chip programme is now visibly multi-pronged. Earlier this week, the company reached an agreement with Qualcomm to supply millions of application-specific integrated circuits for AI data-centre inference. Qualcomm will also help ByteDance bring its own ASIC design through to production.
The company has been instructed by Beijing’s National Development and Reform Commission to reject US-origin capital in funding rounds without clearance. Travel restrictions on senior AI talent that expanded across the private sector this month apply to ByteDance staff, alongside those at DeepSeek, Moonshot, and StepFun. The custom-CPU programme represents the same strategic posture extended into general-purpose server silicon.
The competitive implications for Intel and AMD are significant. The hyperscaler defections of the past five years, including AWS, Microsoft, and Google, have already shifted a meaningful share of the cloud-CPU market away from the x86 incumbents toward custom Arm silicon. ByteDance’s entry, if successful, removes another large customer from the x86 pool. The pricing-pressure spiral runs in both directions: higher x86 prices accelerate hyperscaler custom-CPU adoption, and reduced hyperscaler purchases shrink the volume base over which x86 vendors can amortise their fab costs, which pushes prices even higher.
ByteDance, for its size, is closer to a hyperscaler than to a standard enterprise customer.
What remains unclear is the production-foundry side. Custom CPUs need leading-edge fabrication. TSMC handles most hyperscaler designs at 4nm and below, but US export controls on advanced nodes for Chinese customers complicate the path. SMIC, China’s domestic leading-edge foundry, has reached 7nm in production but lags TSMC by roughly two nodes. ByteDance’s chip programme will have to confront the production-node reality even after it solves the design problem, a part the Reuters reporting did not yet address.
ByteDance has not commented on the design programme or projected first-silicon timelines. The company’s Beijing operations declined to confirm or deny the Reuters reporting.
(Source: The Next Web)
