One PCIe Device Could Triple DDR4 Memory Capacity for Hyperscalers
▼ Summary
– The Marvell Structera X 2404 is a CXL-based memory expander that enables the large-scale reuse of decommissioned DDR4 modules, reducing the need to purchase new DRAM.
– It functions as a PCIe-attached device supporting twelve DDR4 DIMMs per controller, delivering up to 1.5TB of physical memory capacity.
– A key feature is memory compression using LZ4 at line rate, which can effectively double usable capacity, making a 1.5TB pool scale to as much as 3TB.
– A higher-performance variant, the Structera X 2504, uses DDR5 and CXL 2.0 over PCIe Gen5 to provide more bandwidth for deployments needing faster throughput.
– The main technical risk is uncertain latency, as CXL and compression add delay, and a lack of independent testing leaves performance under random read workloads unclear.
Hyperscale data center operators facing rising memory costs now have a promising alternative to purchasing new DRAM. The Marvell Structera X 2404 is a CXL-based memory expander that enables the large-scale reuse of decommissioned DDR4 modules. By installing this PCIe-attached device, operators can leverage older 128GB DIMMs pulled from retired servers to achieve up to 1.5TB of physical memory capacity without investing in new DRAM chips. This approach directly tackles the financial pressure from escalating memory prices by turning existing inventory into a valuable resource.
The device installs into standard server racks as a PCIe card, functioning as an external memory pool rather than a traditional DIMM. It supports four DDR4 channels with three DIMMs per channel, allowing twelve modules to connect to a single controller. This configuration is particularly attractive for hyperscalers who have vast stockpiles of older modules from previous upgrade cycles. From a manufacturing standpoint, it is also efficient, as only the controller, board, and connecting cable need to be produced, not the memory chips themselves.
For environments where cost is the primary driver, the DDR4-focused X 2404 is the solution. However, some operations demand higher performance than older DDR4 can provide. For those needs, Marvell offers the Structera X 2504. This model utilizes DDR5 RAM across four channels and connects via CXL 2.0 over PCIe Gen5. It delivers greater bandwidth by bypassing the CPU’s integrated memory channels, making it suitable for deployments that require faster throughput while still needing expansion beyond the processor’s native DDR5 slot limitations.
A defining feature of both controllers is integrated memory compression. Marvell implements LZ4 compression running at line rate, reporting typical compression ratios between 1.8x and 2x during normal operation. This technology effectively doubles the usable memory capacity. For instance, the 1.5TB physical capacity of the X 2404 can scale to as much as 3TB of usable space. This allows hyperscalers to treat reused DDR4 as a significantly larger and more cost-effective resource than its raw physical size would indicate. Furthermore, it alleviates strain on the DDR5 supply chain, as systems can achieve greater capacity through compression instead of solely buying additional, newer modules.
Despite these advantages, latency remains a critical concern. Independent, real-world testing under diverse workloads has not yet been conducted. The CXL interface inherently introduces some additional delay, and the compression process adds another layer of unpredictability, especially during unpredictable memory access patterns. Without third-party validation of random read latency, it is unclear how these devices will perform under the scattered access patterns common in production systems. Slow response times could negate the benefits of increased capacity. This uncertainty represents the primary technical risk, as latency ultimately determines whether the expanded memory behaves like true main memory or a slower, tiered storage layer.
(Source: TechRadar)
