AMD’s Next-Gen Chiplet GPU: UDNA Revives 2.5D/3.5D Design
▼ Summary
– AMD’s current Radeon RX 9000-series GPUs do not target the high-end market, with the top model competing against Nvidia’s mid-range RTX 5070 Ti.
– Laks Pappu, a senior AMD architect, is leading development for next-gen Radeon and data center GPUs, including Navi4x and Navi5x generations.
– Pappu’s work involves building both monolithic and multi-chiplet-based graphics SoCs, suggesting AMD may use disaggregated designs in future consumer GPUs.
– Multi-tile GPUs for gaming face significant challenges, including latency, synchronization, and software complexity, which have limited their use to data center applications so far.
– AMD’s RDNA 5 architecture, expected in late 2026 or early 2027, is currently in the tape-out phase and may incorporate multi-tile designs if testing proves viable.
AMD’s current Radeon RX 9000-series graphics cards, built on the RDNA 4 architecture, deliberately avoid competing with Nvidia’s highest-end offerings, instead positioning their top model, the Radeon RX 9070 XT, against mid-range competitors like the GeForce RTX 5070 Ti. However, recent insights from a senior AMD engineer suggest the company may be preparing a more ambitious approach for its next-generation GPUs.
According to his LinkedIn profile, Laks Pappu, a senior fellow and chief SoC architect at AMD, is leading development for both data center GPUs and Radeon architectures aimed at cloud gaming, including the upcoming Navi4x and Navi5x generations. His role involves building “next-generation competitive 2.5D/3.5D chiplet-based and monolithic graphics SoCs,” strongly hinting that AMD’s future graphics processors will incorporate both monolithic and multi-chiplet designs.
Pappu joined AMD in August 2022 after more than 25 years at Intel, where he oversaw discrete GPU projects including DG1, Alchemist, and Battlemage. While at Intel, he also explored multi-tile GPU concepts, though current dual-GPU Battlemage products are targeted at AI applications rather than gaming.
High-performance GPU development typically spans 2.5 to 3.5 years from initial architecture planning to final product release. When Pappu arrived at AMD, the RDNA 4 and CDNA 4 architectures were already defined, but he likely played a key role in physical implementation, block configuration, and performance tuning. For the upcoming Navi 5x generation, and potentially the Instinct MI500-series, Pappu is expected to have influence across the full development cycle, possibly introducing advanced 2.5D or 3.5D packaging techniques.
While data center GPUs like AMD’s Instinct MI300 and Nvidia’s Blackwell already use disaggregated designs, consumer graphics cards have largely stuck with monolithic architectures. The tightly coupled nature of graphics workloads makes multi-tile designs particularly challenging. GPUs depend on thousands of parallel threads that must coordinate with minimal latency, and spreading shader cores across multiple dies can introduce synchronization overhead, reduce performance, and increase power consumption.
Advanced packaging technologies like Infinity Fabric or CoWoS help maintain high bandwidth between tiles, but they also raise manufacturing costs and complexity. Additionally, software and drivers must present a multi-tile GPU as a single device to operating systems and game engines, adding further development hurdles. These factors have so far confined multi-tile designs to data center and HPC applications, where the trade-offs are more justifiable.
Still, as building large monolithic gaming GPUs becomes increasingly difficult and expensive, exemplified by Nvidia’s GB102, disaggregated designs may eventually make sense for consumer products. They can improve silicon yields, though advanced packaging introduces its own yield challenges. If AMD can successfully manage compute disaggregation, a multi-tile client GPU could become a reality.
The company has already experimented with chiplet designs in its consumer CPUs and GPUs. The Radeon RX 7900-series, for instance, uses a disaggregated architecture with one graphics compute die (GCD) and six memory/cache chiplets. The symmetrical layout of the GCD even suggests the potential for further logical disaggregation, allowing AMD to create multiple product tiers from a single design.
Pappu’s background at Intel, where he worked on multi-tile “halo” GPUs, combined with his current role, indicates that AMD is seriously exploring this direction for RDNA 5. Timing-wise, AMD typically follows a two-year GPU release cycle. The RDNA 4-based RX 9070-series was delayed to March 2025, making a late 2026 or early 2027 launch window likely for RDNA 5.
As of mid-2025, RDNA 5 is likely in the tape-out or early post-silicon phase, meaning architectural design is complete and physical verification is wrapping up. Performance projections, firmware development, and early driver work are underway internally. Over the coming months, AMD will determine whether a multi-tile design is viable for consumer GPUs based on real hardware testing. This could lead to intriguing leaks and updates as development progresses.
(Source: tomshardware)
